An erasable non-volatile memory device, like other memory devices, comprises a plurality of memory cells arranged in an array of rows and columns with a bit line connecting the memory cells located in each column. Each memory cell includes at least one transistor or other storage device for storing one bit of data.
Some erasable non-volatile memory devices, like the electrically erasable and programmable read-only memory (EEPROM) device described in U.S. patent application Ser. No. 09/124466 (having Attorney Docket No. SC-90891A), entitled `Method and Apparatus for Writing an Erasable Non-Volatile Memory` assigned to the assignee hereof, and the subject matter of which is incorporated herein by reference thereto, require a verification scheme to verify that the memory cells have been written to correctly after a write access (i.e. an erase cycle or a program cycle for EEPROM). Typically this is performed by means of a conventional read cycle. In the case of `smart programming`, after a write access, data is read back from the memory. If the data read back does not match the data to be written to the memory, then another write cycle is initiated. If the data read back does match, then a predetermined number of additional write cycles are initiated. These additional write cycles are required to ensure that the memory has been written to correctly with some margin. However, these additional write cycles can cause stress on the memory cells which may result in the degradation of the programmability of the cell.
There is therefore a need to provide an improved method for verifying data stored in a memory cell after a write cycle which addresses the above problem.